1. Field
Exemplary embodiments of the present invention relate to a redundancy circuit.
2. Description of the Related Art
Sizes of components constituting a semiconductor integrated circuit are getting finer and the number of components included in a single semiconductor chip is significantly increasing, leading to an increase in a defect density. The increase in the defect density may lead to a reduction in the yield of a semiconductor device. In a serious case, a wafer on which a semiconductor device is to be formed may be discarded.
To lower a defect density, a redundancy circuit for replacing a defective cell with a redundancy cell has been suggested. For example, a semiconductor device may include redundancy circuits (or fuse circuits) in each row line (e.g., word line) and each column line (e.g., bit line), and a fuse array may be provided to store address information of defective cells. The fuse array includes a plurality of fuse sets each having a plurality of fuse lines. The fuse set may be programmed by selective laser blowing of fuse lines.
FIG. 1 is a configuration diagram of a conventional redundancy circuit.
Referring to FIG. 1, the conventional redundancy circuit includes a plurality of first block address lines 101, a plurality of first transistors 102, a first fuse array 103, a second fuse array 104, a plurality of second transistors 105, a plurality of second block address lines 106, a plurality of verification lines 107, a plurality of third block address lines 108, a plurality of third transistors 109, a third fuse array 110, a fourth fuse array 111, a plurality of fourth transistors 112, and a plurality of fourth block address lines 113. The above-mentioned components may be disposed in the above-mentioned order starting from the plurality of first block address lines 101 disposed at the top.
First to fourth verification voltage lines 114, 115, 116, and 117 are disposed to be spaced apart from the first to fourth block address lines 101, 106, 108, and 113, respectively. FIG. 2 is a configuration diagram illustrating a 2-stage arrangement of 2-row fuse sets (The respective stages of the fuse sets are identical to each other). The first to fourth fuse arrays 103, 104, 110, and 111 include a plurality of connection fuses 103C, 104C, 110A, and 111A for electrical connection to the verification lines 107.
The operation of the redundancy circuit will be described below with reference to FIG. 1.
Hereinafter, a case that one block address, e.g., an address of a block address line 106A, is activated among the plurality of addresses of first to fourth block address lines 101, 106, 109, and 113 will be described. If the block address is activated, the second transistors 105A and 1058 corresponding thereto are activated. Therefore, the second fuses 104A and 104B included in the second fuse array 104 are electrically connected to the second verification voltage line 115. A verification voltage V1 is applied to the second verification voltage line 115, and a reference voltage V2 is applied to the plurality of verification lines 107.
If the second verification voltage line 115 and the second fuses 104A and 104B are electrically connected together, the voltages of the verification lines 107A and 107B are maintained at the reference voltage V2 when the second fuses 104A and 104B are cut. On the other hand, the voltages of the verification lines 107A and 107B are changed when the second fuses 104A and 104B are not cut (The verification lines 107A and 107B correspond the first and second fuses 104A and 104B, respectively.)
FIG. 2 illustrates the conventional extended redundancy circuit.
Specifically, FIG. 2 illustrates a 4-stage arrangement of 2-row fuse sets. The configuration of a first redundancy unit 201 and a second redundancy unit 202 is almost identical to the configuration of the redundancy circuit of FIG. 1. The first redundancy unit 201 and the second redundancy unit 202 share a fourth block address line 113. A description as to their detailed configuration is omitted, and only lines 101, 106, 107, 108, 114, 115, 116, and 117 and a fuse guard 118 including the fuse array 103, 104, 110, or 111 are illustrated. The connection of the respective components and the internal configuration of the fuse guard 118 are substantially identical to those of FIG. 1. At this time, the lines to which the same serial number is assigned as FIG. 1 indicate that the same signal is applied thereto.
In the conventional art, the first to third block address lines 101, 106, and 108 are repeatedly arranged. In addition, the fuse guard 118 for protecting the fuses from water that may get through from the exterior is formed at every 2-row fuse set. Accordingly, due to the overlapping arrangement of the plurality of block address lines 101, 106, and 108 and the formation of the fuse guard 118 at every 2-row fuse set, a chip area is significantly increased as the number of the stages of the 2-row fuse sets is increased.